Intel builds smallest SRAM cell yet

Last night, Intel announced its first silicon chip success with 90 nanometre processing technology: SRAM memory cells measuring one square micron.

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By  Kate Concannon Published  March 13, 2002

As CeBIT opened the doors of its Hanover residence, Intel announced its latest breakthrough in manufacturing technology: the world’s smallest memory cell has been successfully built using 90 nanometre process technology. Josh Walden, plant manager at Intel’s Ireland Fab24 lab, addressed local journalists today to expand on Intel’s achievement and the implications for industry and end-users.

From these 1 square micron cells, the building blocks of memory chips, Intel researchers created a fully functional SRAM (static random access memory) chip — the industry standard testing vehicle for manufacturing processes. This leap forward signals not only Intel’s healthy pace in the quest to meet Moore’s Law head on, but also the beginnings of a next generation of processors, chipsets and communications products.

Walden stated that Intel is in good shape for achieving its goal to develop chips containing around 1 billion transistors by around 2007, and explained that, just as 0.13 micron technology filtered into chipsets and other products, so too will the newly mastered 90nanometre technology in time.

Made from 300mm silicon wafers, which more than double good chip yield, the SRAM chip has a gate-size of less than 50 nanometres. This translates to higher performance and reduced power consumption. A particularly promising combination for the mobile computing platform, one would think, but Walden told www.itp.net that no plans for implementation of the technology in the production of Banias processors — the first processor to be built bottom-up for notebooks, due 2003 — could be revealed at this stage. It was confirmed, however, that the 90nanometre process will be utilized in the manufacture of Prescott processors.

The wafer created with the 90 nanometre process contains 120 billion transistors, with each chip containing 330 million transistors and 52 megabits on its tiny 109 square millimetre form. Critical layers have been produced using 193nm lithography tools, whereas those layers deemed non-critical use the same 248nm lithography implemented in 0.13 micron technology.

The result: brand new memory cells half the size of those created using 0.13 technology. This, in turn, means more on-die cache memory and higher overall logic density, and so increased processor performance at a reduced cost.

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